/*******************************************************************************
 *                                    ZLG
 *                         ----------------------------
 *                         innovating embedded platform
 *
 * Copyright (c) 2001-present Guangzhou ZHIYUAN Electronics Co., Ltd.
 * All rights reserved.
 *
 * Contact information:
 * web site:    https://www.zlg.cn
 *******************************************************************************/
#ifndef __HC32F4A0_REGS_AOS_H
#define __HC32F4A0_REGS_AOS_H

#ifdef __cplusplus
extern "C" {
#endif  /* __cplusplus*/
#include "core/include/hc32f4a0_regs_base.h"
#include "common/hc32f4a0_common.h"

#define AOS_TMR0_HTSSR_TRGSEL_POS   (0U)
#define AOS_TMR0_HTSSR_TRGSEL       (0x000001FFUL)

typedef struct{
    volatile uint32_t INTSFTTRG;
    volatile uint32_t DCU_TRGSEL1;
    volatile uint32_t DCU_TRGSEL2;
    volatile uint32_t DCU_TRGSEL3;
    volatile uint32_t DCU_TRGSEL4;
    volatile uint32_t DMA1_TRGSEL0;
    volatile uint32_t DMA1_TRGSEL1;
    volatile uint32_t DMA1_TRGSEL2;
    volatile uint32_t DMA1_TRGSEL3;
    volatile uint32_t DMA1_TRGSEL4;
    volatile uint32_t DMA1_TRGSEL5;
    volatile uint32_t DMA1_TRGSEL6;
    volatile uint32_t DMA1_TRGSEL7;
    volatile uint32_t DMA2_TRGSEL0;
    volatile uint32_t DMA2_TRGSEL1;
    volatile uint32_t DMA2_TRGSEL2;
    volatile uint32_t DMA2_TRGSEL3;
    volatile uint32_t DMA2_TRGSEL4;
    volatile uint32_t DMA2_TRGSEL5;
    volatile uint32_t DMA2_TRGSEL6;
    volatile uint32_t DMA2_TRGSEL7;
    volatile uint32_t DMA_TRGSELRC;
    volatile uint32_t TMR6_HTSSR1;
    volatile uint32_t TMR6_HTSSR2;
    volatile uint32_t TMR6_HTSSR3;
    volatile uint32_t TMR6_HTSSR4;
    volatile uint32_t PEVNTTRGSR12;
    volatile uint32_t PEVNTTRGSR34;
    volatile uint32_t TMR0_HTSSR;
    volatile uint32_t TMR2_HTSSR;
    volatile uint32_t HASH_ITRGSELA;
    volatile uint32_t HASH_ITRGSELB;
    volatile uint32_t TMRA_HTSSR0;
    volatile uint32_t TMRA_HTSSR1;
    volatile uint32_t TMRA_HTSSR2;
    volatile uint32_t TMRA_HTSSR3;
    volatile uint32_t OTS_TRG;
    volatile uint32_t ADC1_ITRGSELR0;
    volatile uint32_t ADC1_ITRGSELR1;
    volatile uint32_t ADC2_ITRGSELR0;
    volatile uint32_t ADC2_ITRGSELR1;
    volatile uint32_t ADC3_ITRGSELR0;
    volatile uint32_t ADC3_ITRGSELR1;
    volatile uint32_t COMTRG2;
    volatile uint32_t COMTRG1;
    uint8_t           RESERVED0[76];
    volatile uint32_t PEVNTDIRR1;
    volatile uint32_t PEVNTIDR1;
    volatile uint32_t PEVNTODR1;
    volatile uint32_t PEVNTORR1;
    volatile uint32_t PEVNTOSR1;
    volatile uint32_t PEVNTRISR1;
    volatile uint32_t PEVNTFAL1;
    volatile uint32_t PEVNTDIRR2;
    volatile uint32_t PEVNTIDR2;
    volatile uint32_t PEVNTODR2;
    volatile uint32_t PEVNTORR2;
    volatile uint32_t PEVNTOSR2;
    volatile uint32_t PEVNTRISR2;
    volatile uint32_t PEVNTFAL2;
    volatile uint32_t PEVNTDIRR3;
    volatile uint32_t PEVNTIDR3;
    volatile uint32_t PEVNTODR3;
    volatile uint32_t PEVNTORR3;
    volatile uint32_t PEVNTOSR3;
    volatile uint32_t PEVNTRISR3;
    volatile uint32_t PEVNTFAL3;
    volatile uint32_t PEVNTDIRR4;
    volatile uint32_t PEVNTIDR4;
    volatile uint32_t PEVNTODR4;
    volatile uint32_t PEVNTORR4;
    volatile uint32_t PEVNTOSR4;
    volatile uint32_t PEVNTRISR4;
    volatile uint32_t PEVNTFAL4;
    volatile uint32_t PEVNTNFCR;
} hc32f4a0_aos_regs_t;

#define HC32F4A0_AOS    ((hc32f4a0_aos_regs_t *)HC32F4A0_AOS_BASE)
#ifdef __cplusplus
}
#endif  /* __cplusplus  */

#endif
